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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 25: ISERDES Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
Setup/Hold for Control Lines
T ISCCK_BITSLIP /
T ISCKC_BITSLIP
BITSLIP pin Setup/Hold with respect to
CLKDIV
0.01/0.12
0.02/0.13
0.02/0.15
0.02/0.15
0.02/0.21
ns
T ISCCK_CE /
T ISCKC_CE (2)
T ISCCK_CE2 /
T ISCKC_CE2 (2)
CE pin Setup/Hold with respect to CLK (for
CE1)
CE pin Setup/Hold with respect to CLKDIV
(for CE2)
0.39/–0.02 0.44/–0.02 0.63/–0.02 0.63/–0.02 0.51/–0.22
–0.12/0.29 –0.12/0.31 –0.12/0.35 –0.12/0.35 –0.17/0.40
ns
ns
Setup/Hold for Data Lines
T ISDCK_D /
T ISCKD_D
T ISDCK_DDLY /
T ISCKD_DDLY
T ISDCK_D_DDR /
T ISCKD_D_DDR
D pin Setup/Hold with respect to CLK
DDLY pin Setup/Hold with respect to CLK
(using IDELAY) (1)
D pin Setup/Hold with respect to CLK at
DDR mode
–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.04/0.19
–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.03/0.19
–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.04/0.19
ns
ns
ns
T ISDCK_DDLY_DDR /
T ISCKD_DDLY_DDR
D pin Setup/Hold with respect to CLK at
DDR mode (using IDELAY) (1)
0.11/0.11
0.12/0.12
0.15/0.15
0.15/0.15
0.19/0.19
ns
Sequential Delays
T ISCKO_Q
CLKDIV to out at Q pin
0.46
0.47
0.58
0.58
0.67
ns
Propagation Delays
T ISDO_DO
D input to DO output pin
0.09
0.10
0.12
0.12
0.14
ns
Notes:
1.
2.
Recorded at 0 tap value.
T ISCCK_CE2 and T ISCKC_CE2 are reported as T ISCCK_CE /T ISCKC_CE in the timing report.
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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